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work
simulation for semiconductor manufacturing
topics
wafer-scale AI chips, computational lithography
litho
EUV, 13.5 nm, NA 0.33 / 0.55
posts
1
updated
2026-09-21
lith@1nm:~/me$ cat README.md

Me


I'm lithos12 (@exlithos on X).

I work on simulation for semiconductor manufacturing. Right now that means two things:

  • Wafer-scale AI chips — yield and redundancy modelling, defect maps, power and thermal behaviour across reticle boundaries, cross-reticle interconnect.
  • Computational lithography — OPC, inverse lithography, source-mask optimisation, resist and etch models, and the GPU code that runs them.

Posts here are mostly working notes: derivations, benchmarks, and things I had to figure out the hard way.

elsewhere

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[lithos12]1nm.sirss© 2026 lithos12